960RP in adapter cards

[MMMEI@aol.com]

Hi all-

[Spread Spectrum clocks and their (generally unfavorable) interaction with
PLL based PCI clock regeneration chips have already been discussed here
extensively (look at the archives around July, '96 if interested). /mm]

The 960RP apparently uses internal PLL's and so has a tight maximum jitter
spec. for its PCI clock.  This seems like it is technically PCI non-compliant
in this area.  It also seems like an adapter card which uses this part to
interface to the system PCI bus would run into problems with systems using
spread spectrum clocks to control EMI. (This should only be an issue for
add-in card designs because the card has no control over the clock
characteristics of the primary PCI bus; in a motherboard design using the
960RP, the problem would not be relevant because the PCI clock
characteristics could be controlled by design.)

I'm currently designing an adapter card around this chip.  I'm debating
whether to just ignore this issue and interface the 960RP directly to the
system bus, or to add a separate PCI-PCI bridge chip between the 960RP and
system.  A separate bridge would allow me to clock the card's local PCI bus
at a constant 33Mhz, but it adds considerable expense and complexity to the
design.  Also, I've yet to find a bridge which allows each side to be
independantly clocked.  Any other developers out there willing to share their
approaches?

Thanks in Advance,

-Mike Martin
Millennium Engineering, Inc.

P.S. Apologies for this 'silicon specific' post, but the underlying issues
may be relevant to other products also.
šàÏ