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Re: Approaches for PCI Overvoltage design using 3.3volt technology

>  The PCI specification requires an input to be able to handle a 11 volt   
>  overvoltage waveform in a 5 v signaling environment.  I've noticed that a   
>  number of manufacturers have developed PCI chips based on 3.3 volt   
>  technology that claim to have 5 volt tolerant inputs, while at the same   
>  time give absolute maximum ratings much less than 11 volts.
>  I was wondering how designers out there are handling this problem...

Isn't this usually handled by the clamp diodes?  In fact, even if the
process doesn't include diodes per se, it seems like you will forward
bias the p channel of the output transister with respect to either the
n well or an n substrate.  So, if you read that section of the spec
carefully, you will even see a couple of reminders that the voltage at
the package pins is "greatly reduced" ( because of the clamps.
The spec is REALLY saying that you have to deal with 0.120 mA through
your, say, 0.7 volt clamp with a duty cycle of about 15%;  this is 12.6