RE: Approaches for PCI Overvoltage design using 3.3volt technology

[Alan Yee <alany@Aureal.com>]

From:  Andy Ingraham[SMTP:ingraham@wrksys.ENET.dec.com]

 --snip question on overvoltage in 5 volt signaling environment +   
explanation about devices limiting voltage.

>> I was wondering how designers out there are handling this problem in   
3.3
>> volt technology designs.  Are you designing only for a 3.3 volt   
signaling
>> environment?  Are you designing special I/O buffers which are actually   
11
>> volt tolerant?  Are you ignoring this part of the spec altogether?

 --snip response about nobody designing only for 3.3 volts + explanation   
of overvoltage waveform and clamp diodes for ESD

>Overshoot clamps, though not required in PCI's 5 V signaling
>environment, are highly desirable.  The PCI Spec even points out that
>they are probably necessary in practice when using 3.3 V components on
>the 5 V bus.  You do need to be careful about how you implement them,
>though; you can't just clamp to the 3.3 V rail.

>Regards,
>Andy Ingraham

Are you saying that most designers use large series resistors (say on the   
order of 1k) and protection diodes to the 5 volt rail to limit the   
current and voltage respectively in their designs?  It would seem that   
diodes alone would require a large number of 5 volt pins to sink the   
current back into the board since the current would be on the order of   
~90mA. Per pin.  The addition of large series resistors would seem to add   
problems elsewhere (undesirable propagation delays, current limiting on   
the outputs etc.)

Alan
´`
M