Re: Approaches for PCI Overvoltage design using 3.3volt technology

[Andy Ingraham <ingraham@wrksys.ENET.dec.com>]

> Are you saying that most designers use large series resistors (say on the   
> order of 1k) and protection diodes to the 5 volt rail to limit the   
> current and voltage respectively in their designs?  It would seem that   
> diodes alone would require a large number of 5 volt pins to sink the   
> current back into the board since the current would be on the order of   
> ~90mA. Per pin.  The addition of large series resistors would seem to add   
> problems elsewhere (undesirable propagation delays, current limiting on   
> the outputs etc.)

You are right; you can't just add diodes from all PCI pins to a single
5 V pin and expect it to work.  In addition to the ~90 mA per pin
times 45 pins, the inductance of the one 5 V pin would make it an
ineffective clamp when the whole bus switches low-to-high at once.

Large series resistors wouldn't work on I/O pins because as outputs
they wouldn't have enough drive and wouldn't meet the I/V curves
anymore.  Anyway, you might not want that +11 V anywhere on your chip,
not even on the bondwire pads.  Maybe the technology won't support 11
volts anywhere on the chip.

So you need to be more creative.

Something like a zener diode from each pin to ground might work.

By the way, also note that ordinary CMOS outputs (n-channel to VSS,
p-channel to VDD) are NOT suitable as 5 V compatible I/O's with 3.3 V
technology parts where the VDD is 3.3 V.  This gives you a parasitic
clamp diode from the I/O pin to the 3.3 V supply, which is not OK.
Again, you have to be creative.

Regards,
Andy Ingraham
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