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PCI Prefetchable Memory
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: PCI Prefetchable Memory
- From: Eric Rehm <eric@equator.com>
- Date: Fri, 28 Feb 1997 13:43:14 -0800
- Resent-Date: Fri, 28 Feb 1997 13:43:14 -0800
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"e31NX3.0.LN.17r5p"@dart>
- Resent-Sender: pci-sig-request@znyx.com
* Do Intel's current x86 Host-PCI bridges in their core logic chip sets make
use of PCI prefetchable memory when core logic is the PCI bus master?
* If so, does Intel's Host-PCI logic implement MemReadLine and MemReadMultiple
by being smart, i.e., sees x86-originated programmed I/O to PCI prefetchable
targets?
/eric
Equator Technologies, Inc.
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