PCI PM wakeup from D3 Cold

[pontius@west.smc.com (Mark Pontius x4805)]

I believe I've found a problem with the 0.99a rev of the PCI Power Management
spec, (Figure 7).

Devices in D3cold are expected to transition to D0 uninitialized upon PCI RST#.
What happens on this signal during VCC removed?  I assume it will drop to 0V
along with the rest of the bus (unless the system actively drives it low).
Either way, the device (powered off an auxiliary supply) sees RST# asserted
and tries to transition to D0 uninitialized immediately while power is still
off!

Here's what I'm guessing will happen on the VCC and RST# lines:

VCC  ~~~~~\_____________/~~~~~~~
RST# ~~~\__________________/~~~~
     ^     ^                ^
     D3hot |                |
           D3cold           |
                            D0uninitialized

If this is the case, the transition from D3 to D0uninitialized should occur
when RST# goes high, not when it is asserted.

Perhaps a better solution would be for the device to stay in D3 (as part of
maintaining PME Context), requiring the OS to switch it back to D0.

Does anyone have a better solution?

--Mark Pontius
  SMC
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