re: PCI PM polarity of PMCSR bit

[Brian Belmont <a0192894@decmail.itg.ti.com>]

>  From: pontius@west.smc.com (Mark Pontius x4805), on 3/10/97 11:43 AM:
>  The value written to the PMCSR register required to clear the PME_Status has
>  inverted between the 0.90 and 0.99a releases of the PCI Power Management 
>  Spec.
>  
>  The PMCSR register, bit 15, PME_Status:
>          v0.90: Writing a 1 to this bit will clear it
>          v0.99a: Writing a 0 to this bit will clear it
>  
>  Why was this changed?  Was it a typo?
>  I believe the 0.90 method is more logical, since PCI already uses the
>  mechanism of writing a 1 to clear status in the interrupt register: config
>  space, address 4 (text on bottom of pg 191 in the PCI rev 2.1 spec).
>  
>  --Mark Pontius
>    SMC

The PME_Status bit was erroneously inverted in the 0.99a version of the PCI
Power Management spec.  The bit has been changed back to it's original polarity
(as documented in v0.90) and this change will be reflected in the next posting
of the specification which should be the official version submitted for the SIG
30-day review.  

The Power Managment Working group apologizes for any confusion generated by
this oversite.  Again, the correct version will follow the PCI precedent and
writing a 0 to this bit will clear it (Bit 15 of PMCSR).
  
Thanks,
Brian Belmont		Voice: 	972.997.6021
Texas Instruments	Fax:	972.997.6301
PC Systems Lab		MsgID:	BVB1
					Internet: bbelmont@ti.com
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