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PCI PM polarity of PMCSR bit
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: PCI PM polarity of PMCSR bit
- From: pontius@west.smc.com (Mark Pontius x4805)
- Date: Mon, 10 Mar 97 11:43:30 PST
- Resent-Date: Mon, 10 Mar 97 11:43:30 PST
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"DgpAP3.0.bI1.9I69p"@dart>
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The value written to the PMCSR register required to clear the PME_Status has
inverted between the 0.90 and 0.99a releases of the PCI Power Management Spec.
The PMCSR register, bit 15, PME_Status:
v0.90: Writing a 1 to this bit will clear it
v0.99a: Writing a 0 to this bit will clear it
Why was this changed? Was it a typo?
I believe the 0.90 method is more logical, since PCI already uses the
mechanism of writing a 1 to clear status in the interrupt register: config
space, address 4 (text on bottom of pg 191 in the PCI rev 2.1 spec).
--Mark Pontius
SMC
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