PCI CLK CONSTRAINTS

["JAMES MURRAY" <james_murray@SpectrumSignal.com>]

     Hello
     
     I am designing an ASIC with a 2.1 compliant PCI master/slave 
     interface, using one of the "popular" off-the shelf PCI cores.
     
     I have 2 questions regarding the SYNOPSYS synthesis constraint files 
     supplied with the core, regarding the way in which the PCI clock is 
     specified. I was hoping someone could comment on my assumptions below.
     
     
     
     Issue 1:   The PCI clock is described as having a duty cycle of 50%.
     
     If I look at the PCI spec, I see that the minimum clock low time is 
     11ns and the minimum clock high time is 11ns. Does this not mean that 
     the worst case PCI clock duty cycle is only 37%? (11/30)
     
     Issue 2:   The PCI clock is described as having an uncertainty of 0ns.
     
     The PCI spec states that the minimum clock slew rate is 1V/ns and the 
     maximum slew rate is 4V/ns. I assume that this would imply a clock 
     "uncertainty" of 1.5ns worst case. (Threshold 1.5V at 5V)
     
     Thank you in advance for any feedback
     
     
     James Murray
Õ4
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