Re: PCI PM polarity of PMCSR bit

[Gary Solomon <Gary_Solomon@ccm.jf.intel.com>]

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     Mark,
     
     The 0.99a spec has a typo for clearing out the PME_Status bit.  Good 
     catch.  The correct way to clear this rd/wr-clear bit is to write a "1" 
     to it.  It's been updated in the latest working revision.
     
     Thanks,
     
     Gary Solomon
     Platform Architecture Lab - Intel
     
     
______________________________ Reply Separator _________________________________
Subject: PCI PM polarity of PMCSR bit
Author:  Brad W Hosler at JFCCM7
Date:    3/10/97 1:45 PM
     
     
The value written to the PMCSR register required to clear the PME_Status has 
inverted between the 0.90 and 0.99a releases of the PCI Power Management Spec.
     
The PMCSR register, bit 15, PME_Status:
     v0.90: Writing a 1 to this bit will clear it 
     v0.99a: Writing a 0 to this bit will clear it
     
Why was this changed?  Was it a typo?
I believe the 0.90 method is more logical, since PCI already uses the 
mechanism of writing a 1 to clear status in the interrupt register: config 
space, address 4 (text on bottom of pg 191 in the PCI rev 2.1 spec).
     
--Mark Pontius
  SMC

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Subject: PCI PM polarity of PMCSR bit
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From: pontius@west.smc.com (Mark Pontius x4805)
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