Re: PCI PM wakeup from D3 Cold

[Gary Solomon <Gary_Solomon@ccm.jf.intel.com>]

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     Mark,
     
     For add-in cards that have an auxiliary voltage source, the assumption 
     is that the card itself can effectively determine the presence, or 
     absence of the main Vcc source to the slot.
     
     Given that, the design should be able to differentiate between a power 
     up reset sequence vs. a powered down bus with RST# potentially low, 
     and act accordingly.
     
     Make Sense?
     
     Gary Solomon
     Platform Architecture Lab - Intel


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Subject: PCI PM wakeup from D3 Cold
Author:  pontius@west.smc.com at SMTPGATE
Date:    3/10/97 11:32 AM


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From pontius Mon Mar 10 11:21:04 1997 
To: pci-sig@znyx.com
Subject: PCI PM wakeup from D3 Cold
Content-Length: 1081
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I believe I've found a problem with the 0.99a rev of the PCI Power Management 
spec, (Figure 7).
     
Devices in D3cold are expected to transition to D0 uninitialized upon PCI RST#. 
What happens on this signal during VCC removed?  I assume it will drop to 0V 
along with the rest of the bus (unless the system actively drives it low). 
Either way, the device (powered off an auxiliary supply) sees RST# asserted
and tries to transition to D0 uninitialized immediately while power is still 
off!
     
Here's what I'm guessing will happen on the VCC and RST# lines:
     
VCC  ~~~~~\_____________/~~~~~~~
RST# ~~~\__________________/~~~~
     ^     ^                ^
     D3hot |                |
           D3cold           |
                            D0uninitialized
     
If this is the case, the transition from D3 to D0uninitialized should occur 
when RST# goes high, not when it is asserted.
     
Perhaps a better solution would be for the device to stay in D3 (as part of 
maintaining PME Context), requiring the OS to switch it back to D0.
     
Does anyone have a better solution?
     
--Mark Pontius
  SMC
     
     
     
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Subject: PCI PM wakeup from D3 Cold
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