PCI DMA under Windows NT

[jones%photon@cti-pet.com (Bill Jones)]

Dear PCI SIG folks,

Thanks for the opportunity to connect to this reflector. 

We are making medical scanners here. Please check out our web page.

Currenly moving to get our 40 Mbyte/sec stream of nonreproducible 
patient scan data onto PCI and out to a 72 Gbyte RAID system. This 
requirement probably means we'll have to design our own optimized 
PCI card to DMA the data stream into PCI. Have bought an Emulex 
Light Pulse Host Bus Adapter and a Ciprico 72 Gbyte RAID.

Our data stream is to arrive at our PCI card via fiber optic link 
and locally load a FIFO. We'll need to get that FIFO data to RAID 
over the PCI bus.

We are just beginning to understand the scope of this undertaking. 
Just starting to understand the difficulty presented to fast DMA 
hardware under Windows NT. There seem to be two primary problems:

 1) Windows NT is not real time. We are told to expect periods of 
    from 5 to 100 ms where the Pentium processor will not respond 
    to interrupts. 

 2) Windows NT is virtual memory mapped. Assigning the 
    physical memory address to the DMA hardware may force 
    heavy fragmentation of the DMA transfer and require chaining 
    for fast sustainable throughput.

Our application makes both of these problems difficult from one 
extra standpoint. We cannot afford to loose any of our stream. 
If we start off transferring at 40 Mbytes/sec, we'd like to not 
have periods where NT does not keep the DMA transfers going. 
If this happens we've lost a chunk of our patient-in-the-scanner 
data. 

Do we:

 1) Plan for our DMA to go to PC motherboard DRAM in a couple of 
    software defined 4 to 16 Mbyte buffers? If we go this way, may we 
    expect Windows NT to allocate contiguous 16 Mbyte chunks of 
    DRAM space? Or, will we be forced to do DMA chaining with 
    multiple DMA control blocks resident on local static RAM? Or 
    may we expect to do nicely with a pair of prioritized DMA 
    channels, each one able to transfer an entire 4 Mbyte chunk 
    and able to start automatically when the other finishes.

OR

 2) Design 16 Mbytes of DRAM onto our DMA card and let the Light
    Pulse DMA out of our DRAM? A lot of extra hardware design.

OR

 3) Plan for our DMA to write to the 128 Kbyte Static RAM buffer 
    on the Light Pulse card? This seems likely to fall short.

Any guideance you can offer will be appreciated.

Regards,

Bill
_______________________
Bill Jones
Senior Development Engineer
CTI PET Systems, Inc.
810 Innovation Dr.
Knoxville, TN 37932-2571
voice: 423 966 0072 x254
fax: 423 966 8955
email: jones@cti-pet.com
web: www.cti-pet.com
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