PCI Arbiter Chips

["David O'Shea" <daveo@corollary.com>]

Does anyone know of a nice PCI arbiter in a chip without much else?
Does anyone have experience with an FPGA pre-canned arbiter design
in place of a fixed silicon design?

I am looking for an arbiter with the following features:

1. Support for 5 Masters.
2. 2 Priority levels (or more).
3. Leaves GNT# asserted to current master when no REQ# asserted.
   (This prevents Latency timer from kicking in for no reason).
4. Programmable cycle holdoff for RETRY'd masters before GNT# will
   be awarded to RETRY'd master again.
5. Bus Parking on a selected Master (which can be a fixed REQ) when the
   bus is in the idle state.

It's a big shopping list, so I would love to hear about any arbiters that
people have experience with.  

Respond to me directly and I will post a summary, or just send it to 
the reflector....

Thanks,
David O'Shea
daveo@corollary.com
Principle SW Engineer
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