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Floating 64bit extension signals on a parked bus
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Floating 64bit extension signals on a parked bus
- From: "Thomas R. Hotchkiss" <tomh@giga-net.com>
- Date: Fri, 28 Mar 1997 12:30:46 -0500
- Cc: "Roman, Harold" <harold@coke.giga-net.com>
- Organization: GigaNET, Inc.
- Resent-Date: Fri, 28 Mar 1997 12:30:46 -0500
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"ypJLO3.0.lc4.1-_Ep"@dart>
- Resent-Sender: pci-sig-request@znyx.com
- Sender: tomh@coke.giga-net.com
PCI Experts-
While working on an ASIC that is 64bit capable, we encountered the
following two questions that we have been unable to answer definitively
by reading the rev 2.1 spec.
1. On a bus that is 64bit capable, and has been reset with 64bit
enabled, what happens to the 64bit extension signals (AD[63:32],
C/BE[7:4]#, PAR64) when the bus is parked on a device that is only 32bit
capable?
Our assumption is that these signals will be tri-stated, but then they
may be floating for a long period of time, which could be a problem.
Another possibility is that the central resource is smart enough to know
not to park the bus on a 32bit device on a bus that has also has 64bit
devices, but this seems complicated. Anybody know what happens in this
situation?
2. When a master starts a write transaction with REQ64# asserted, and
the target responds but does not assert ACK64#, what should the master
do with AD[63:32], C/BE[7:4]# and PAR64? It seems best if the master
drives these signals to some arbitrary value, but one reference book we
have (not the spec) implies that the master should tri-state the
signals. If the master drives the signals, does parity need to be
correct?
Any help would be greatly appreciated,
Tom Hotchkiss
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