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'Old PPB' and 3.3.V signaling compatibility
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: 'Old PPB' and 3.3.V signaling compatibility
- From: vch@cetia.fr (Vincent CHUFFART)
- Date: Wed, 2 Apr 1997 10:36:02 +0100 (NFT)
- Cc: vch@cetia.fr (Vincent CHUFFART)
- Reply-To: Vincent.Chuffart@cetia.fr
- Resent-Date: Wed, 2 Apr 1997 10:36:02 +0100 (NFT)
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"cBLO-3.0.04.tSeGp"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Beware, this hardware question does not come from a hardware guy!
We do have a DEC21050 on one of our VME motherboard design.
One of our customer would like to know wether the use of a 3.3V
PCI chip on the secondary bus of the 21050 is feasible ?
He says his chip will have 5V compatible input pads. So far so good, but
what about 3.3V signaling from this chip going TO the Dec 21050 input pads ?
What type of behaviour shall we expect ? Is a CMOS 1 generated by a 3.3V
signaling device always good enough to be seen as a 1 from a 5V input pad ?
Anything strange on transients ?
Note: the secondary bus will be loaded with a few 'equivalent charges'
(5 at most, vs the usual max of 10-loads-rule-of-thumb).
NOTE: most of the new DEC PPB product are now said to be 3.3V signalling
compatible. So what was missing in the old 21050 ?
Thanks for your help.
Vincent.
--
Vincent H. Chuffart _/_/_/ _/_/_/ _/_/_/ _/ _/_/ CETIA BP 244
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