Re: 'Old PPB' and 3.3.V signaling compatibility

[Simon Cameron <Simon.Cameron@vsl.com.au>]

At 10:36 AM 2/04/97 +0100, you wrote:
>
>Beware, this hardware question does not come from a hardware guy!
>
>We do have a DEC21050 on one of our VME motherboard design.
>One of our customer would like to know wether the use of a 3.3V
>PCI chip on the secondary bus of the 21050 is feasible ?
>
>He says his chip will have 5V compatible input pads. So far so good, but
>what about 3.3V signaling from this chip going TO the Dec 21050 input pads ?
>What type of behaviour shall we expect ? Is a CMOS 1 generated by a 3.3V
>signaling device always good enough to be seen as a 1 from a 5V input pad ?
>Anything strange on transients ?

My understanding is that 3.3V and 5.0V TTL logic have the some voltage
thresholds. Therefore a logic '1' driven by a 3.3V driver will be seen as
a logic '1' by the 5V receiver => no problem.

A logic '1' driven by a 5V driver may however exceed the maximum input
voltage of a 3.3V receiver (normally Vcc + 0.3V = 3.6V). Therefore the
3.3V receiver could be damaged by the 5V drive levels. In your case
the 3.3V chip has 5V compatible input pads => maximum input voltage will
be > 5V, so again there is no problem.

(I am currently designing a board which has a 3.3V device with 5V compatible
inputs on a 5V PCI bus, but I have not tested it yet.)

>Note: the secondary bus will be loaded with a few 'equivalent charges'
>(5 at most, vs the usual max of 10-loads-rule-of-thumb).
>
>NOTE: most of the new DEC PPB product are now said to be 3.3V signalling
>compatible. So what was missing in the old 21050 ?

This suggests to me that the DEC PPB must drive the PCI bus with 3.3V
signal levels and has 5V compatible inputs.

>Thanks for your help.
>Vincent.
>-- 
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Regards,
Simon.
------------------------------------------------------------------------
Simon Cameron
Electronic Design Engineer

Vision Abell Pty Ltd			Tel:    +61 8 8300 4400
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Technology Park				Email:  Simon.Cameron@vsl.com.au
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