Re: PCI DMA controller

["David O'Shea" <daveo@corollary.com>]

>>David O'Shea wrote:
>> 
>> For writes, you can get "some" bursting.   This is really achieved
>> by the CPU bus to Host bus bridge when it occurs.  Again, the
>> rep movsd performs individual writes of 32 bit quantities.    These
>> writes really go to the "CPU bus -> PCI bus bridge" where they are
>> posted temporarily.  While the bridge arbitrates and wins the PCI
>> bus and proceeds to transfer, the CPU is transferring another 32 bit
>> DWORD in another transaction.  If the CPU is fast enough, or the bridge
>> slow enough, the posting buffers can fill up in the bridge, and then
>> when the bridge wins the PCI bus, it will perform a burst transaction
>> of the merged posted DWORDS to the PCI bus.   This can give short
>> bursts on writes.
>> 
>> David O'Shea
>> daveo@corollary.com

>Later, At 02:07 AM 3/30/97 -0800, arthur blank wrote:
>I was reading your response and was puzzled by your explanation in the
>above paragraph.
>
>On individual writes, couldn't the memory address change from one write
>to the next, in a non sequential fashion?  If this happened how would
>the bus bridge know which address to write to on the PCI bus, unless it
>also posted the address for each transfer?  If this is the case, it
>seems to me the bridge would require an awfully wide posting buffer
>storing both data and addresses.
>
>Arthur Blank

Bridges also posts the address for each transfer.  A typical host bridge that
has posting buffers (say a Typical Intel Host bridge) has 4-8 posting buffers
that will hold address and data.   As you implied above, if sequentially
posted writes are not to adjacent addresses, then burst combining is not
done.  In practice, if adjacency does occur, and the bridge is configured
for combining, then combining does take place.   Often, this is one of the
first features to be disabled by BIOS developers, because chipset manufacturers
often find that they have logic problems in the post buffer combining logic.

Host bridges already have to store the address in a posting buffer, even 
if the buffers will not be used for combining, if they are to have more than
one posting buffer.   All Intel bridges since the 82420 chipset have had
at least four posting buffers.   These buffers make a huge difference in the
performance of the Host bus, which is why the large register space is 
designed into these bridges.   Unfortunately, in first, second, and sometimes
third cuts of these chip sets, the posting buffer logic is often flawed in
some subtle manner, requiring that the posting feature be entirely disabled.

I can't actually give any details about what works and what does not since
a) I would probably be inaccurate. b) my employer probably has signed an NDA
saying that I would not talk about any Intel errata.  We've probably signed
an NDA saying we would not talk about the NDA, so I'm probably already in
trouble.

The PCI specification allows for more advanced combining than I have 
described here.  If two addresses are not continguous, they could still
be combined into a burst.  The bridge just sets the byte enables for the
intermediate words to none-enabled until the later address comes up in the
burst.  I have not seen any bridges that actually implement such fancy
post-combined, gap-byte-disabled-bursting.  It seems orders of magnitude
more difficult, for little gain.   The chip set people are having a hard
enough time getting the more simple posting to always work correctly.

A description of the posting logic in an Intel Host bus bridge is not
a giant secret.  Look in any Intel data book that contains a host bus bridge.
I would say that looking in OLDER databooks for older chip sets is better.
For instance the 82430 chip set is reasonably well documented.  If you can
get your hands on a 1995 or later "Peripheral Components" Intel databook.
Newer chip sets have the same sorts of logic, but often the behavioral
desciption is no longer included in the public versions of the databooks.
If you  do not have some idea what features are in the chip sets, its
hard to make much from the bit descriptions that are listed in the newer
databooks.

So, yeah, addresses are posted as well, and the post buffers are really wide.

-David O'Shea
daveo@corollary.com


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