PCI to PCI Dec Bridge specification

[Guy Bonneau <guy.bonneau@Matrox.COM>]

Hi,

I am trying to understand the meaning of some control chip bits in the DEC
pci to pci bridge (DECchip 21052) . Unfortunately the meaning of those bits
are unclear to me. The bits are located in a control register of the DEC
bridge. The control register is located at offset 0x40 of the PCI
configuration space. The name of that register is Chip Control/Diagnostic
Control/Burst Limit Counter/serr Disable Register. The bits I am trying to
understand are <3:2> of the Chip Control. The specification say about those
bits:

Request mask timer. Designates the maximum value of the request mask timer,
which is enabled after the 21052 issues a target retry to a master on the
secondary bus. 

Default value is 0.

00b-mask timer not used
01b-16 PCI clock cycles
10b-32 PCI clock cycles
11b-64 PCI clock cycles

Unfortunately I do not understand what the specification say but I know
that I have been able to improve the behavior of pci transfers between the
primary and secondary bus when reprogramming those 2 bits to 11b. The
improvement occurs when the CPU trough the host bridge on primary bus is
trying to read registers on a pci device on secondary bus while at the same
time another device on the secondary bus is trying to write through burst
transactions to system memory. The DEC bridge sits between the primary bus
and the secondary bus. 

But I do not know why I have improvement because I am baffled by the
meaning of those 2 bits.

Anybody can give me the clue to the meaning of those 2 bits?

Thanks,
Guy Bonneau



______________________________________________________________________

 Guy Bonneau,                         
 Senior Software Engineer,             Email : Guy.Bonneau@matrox.com
 Video Products Group                  voice : (514) 685-7230 X-2718
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