YMMV - Sustained transfer rates on Intel 430VX motherboard

[bsugar@ambex-boulder.com (Bob Sugar)]

Hi,

I'm working on an PCI expansion card and am having trouble reaching
reasonable
transfer rates even when running large (4KB) master-mode transfers.  The
best
that I can get when running with a 430VX motherboard is ~45 MB/sec read
and
~61 MB/sec write.  After looking at the PCI bus with an analyzer, I find
that
the motherboard (aka the target) is transferring 8 words and then
disconnecting.
The bus then sits idle for a while, my card re-arbitrates, and then the
transfer continues after a bunch of idle cycles and wait cycles.  There
is essentially
nothing else running on the test PC (except DOS).

According to Bruce Young's post from last summer (attached), I should
rarely
see a target disconnect with Intel's more recent chip sets and that
sustained
rates of over 100MB/sec are possible.

I've tried reprogramming the latency timer, the cacheline size register,
and
even some of the VX registers (including the Multi-Transaction Timer)
but can't
get anywhere close to Bruce's numbers.

What am I doing wrong???


Thanks,

Bob Sugar
Sr. Systems Engineer
AmBex Technologies, Inc.
Boulder Colorado


Bruce Young wrote:
> 
> ---------------------------- Forwarded with Changes ---------------------------
> From: pci-sig-request@znyx.com at SMTPGATE
> Date: 7/31/96 9:00AM
> *To: pci-sig-request@znyx.com at SMTPGATE
> Subject: motherboard target burst size
> -------------------------------------------------------------------------------
> 
> Text item:
> 
> Motherboards based on the 82430FX, HX & VX chipsets (formerly known as Triton or
> TritonII) for Pentium(R) as well as the 82440FX chipset for Pentium Pro should
> be able to handle read or write bursts to memory of up to 4 kbytes. The only
> time you should see the chipset disconnect on a write is on 4k page boundaries.
> The 430 family of chipsets will only disconnect reads on 4k page boundaries as
> well. The 440FX will disconnect a plain old Memory Read at the first cache line
> boundary. The 440FX may also disconnect MRL & MRM at cache line boundaries due
> to extremely heavy CPU bus congestion but will almost always allow them to
> continue until a 4k page boundary. The 440FX behaves differently than the 430
> family due to the increased complexity of the Pentium Pro bus.
> 
> Depending on the chipset and the state of the cache for that location, there
> might be a small number of wait-states inserted at cache line boundaries but in
> general there will be no wait states between cache lines.  As I recall, this
> should hold true for either EDO or FPM memory as well as SDRAM (supported only
> by the VX). I don't remember the exact lead-off delays but as I recall, it is in
> the 3-4 clock range for writes and 8-12 clocks for reads although it may be
> higher if a modified cache line is accessed.
> 
> We have demonstrated sustained PCI to DRAM access in excess of 100 MB/s for each
> of these chipsets although a real application sharing the bus with other devices
> will not be able to attain that in most instances.
> 
> The older 430LX and NX chipsets (formerly known as Mercury and Neptune) will
> always disconnect on cache line boundaries and for writes, will limit the burst
> length to 4 DWORDS. This means that the maximum PCI to DRAM bandwidth for these
> old chipsets is about 40 MB/s.
> 
> Bruce Young
> Intel Corporation
> On the net I speak for myself, not Intel.
€p