FW: YMMV - Sustained transfer rates on Intel 430VX motherboard

["Rosenthal, Hanan" <Hanan_Rosenthal@cisnc.canon.com>]

>
>Gentlemen,
>
>The bottleneck in these cases could well be the host-to-PCI bridge.
>Intel host bridges contain buffers that should support burst read and write
>transactions by a PCI master to and from main memory, including prefetching
>in case of burst reads from memory. However, the buffers must be enabled in
>order to take advantage of this feature. This means setting some control bits
>in the device- specific configuration space.  
>Many BIOSes disable the burst transaction support as a part of the initial
>setting. If one tries now to burst-read data across the host bridge, the
>bridge issues a "disconnect" sequence after each transfer, since it needs to
>get the next item from the host bus. 
>To achieve high rates, the application must make sure that the PCI read/write
>control register(s) in the host bridge are set to enable burst support. After
>that there may still be more tuning needed (e.g. Bus arbitration priorities).
>
>Hope this helps...  
>
>Hanan 
>
>
>----------
>From: 	Bender, Bernhard[SMTP:br@elsa.de]
>Sent: 	Wednesday, April 09, 1997 6:53 AM
>To: 	Mailing List Recipients
>Subject: 	Re: YMMV - Sustained transfer rates on Intel 430VX motherboard
>
>well...
>
>I also wonder why bus master transfer rates are so low with PCI chip 
>sets from intel. on a typical PPro system I often observe transfer 
>rates as low as 20 MByte/s. The bus master is otherwise able to 
>accept 80+ MB/s as a target.
>
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>
>
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