Question: Noise margin in 3V3 signaling ?

[basset@csti.fr (Thierry Basset)]

Hi,

i have a question about noise margin in 3V3 signaling.

I suppose two 3V3 components on the PCI bus, powered or not from
 the same 3V3 supply.

Standard configuration: 
----------------------
The emitter and the receiver are powered from the same 3.3V supply.
The lowest supply can be 3.0V.

3.0V                                              3.0V
    +-----+ out                       in  +-------+
    |     |------------------------------>|       |
    |     |                               |       |
    +-----+                               +-------+
      (VoH)min = 0.9*Vcc         (ViH)min = 0.5*Vcc
               = 2.7V	                  = 1.5V

=> the noise margin is 2.7 - 1.5 = 1.2V.


Worst configuration: 
--------------------
The emitter and the receiver are not powered from the same 3.3V supply.
The lowest supply can be 3.0V, and the highest one 3.6V.


3.0V                                              3.6V
    +-----+ out                       in  +-------+
    |     |------------------------------>|       |
    |     |                               |       |
    +-----+                               +-------+
      (VoH)min = 0.9*Vcc         (ViH)min = 0.5*Vcc
               = 2.7V	                  = 1.8V

In this case, the  noise margin is reduced to 0.9V.



Question:
---------
Is this reduced noise margin acceptable? (i think so).
Are these 1.2V an absolute minimum on which the PCI 2.1 specification
is built (I don't think so) ?
If so, it would imply that you must powered the emitter and the receiver
(their IO buffers at least) from the same 3V3 power. This seems not viable 
to me.

Any comments ? 

		Thierry Basset.


******************************************************************
Thierry BASSET 	
Board Designer - Hardware Engineer
Compagnie des Signaux Technologies Informatiques.

CSTI 		
1, bd Marius Vivier Merle
69443 Lyon cedex 03 - FRANCE

Tel: (33) 4 7235 8479
Fax: (33) 4 7235 8425
email: basset@csti.fr
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