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Re: Claiming 1M when using 8K
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Claiming 1M when using 8K
- From: Alan Deikman <alan@znyx.com>
- Date: Wed, 16 Apr 1997 14:12:34 -0700
- Resent-Date: Wed, 16 Apr 1997 14:12:34 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"1h0lJ2.0.xq3.T4KLp"@dart>
- Resent-Sender: pci-sig-request@znyx.com
>Well, you can't make the I/O Bar request 1MB of I/O space because
>that's illegal now. The 2.1 spec changed things for I/O space so that
>now you can't allocate more then 256 bytes! for an I/O bar. In 2.0
>this was just a recommendation. (The recommendation was an excellent
>one for PC's, but the requirement is somewhat stupid for everyone
>else, >and 2.1 should have never made it a requirement, but..... they did
>so 256 bytes is the law of the land now for I/O.)
Remember that I/O support was mostly a concession to PC's and x86
architecture to begin with. What bulk-RAM-access (multiple Kbytes or
more) application is better served with I/O instructions as opposed
to memory access instructions anyway?
I see more architectures these days that don't even bother to implement
an I/O space at all. Why waste the gates on the chip for it when all
it does is add another resource category for the OS to deal with? The
only reason I can think of is because the 4004 had it.
If I had been specifying PCI at the start I would have been tempted
to do away with I/O transactions altogether, and simply have the
CPU-to-PCI bridges deal with the translations for those CPU
architectures that require (want) it.
--------------------------------
Alan Deikman, ZNYX Corporation
alan@znyx.com
3 Ø Æ