Target Initial Latency: How to count clocks?

[pavel.peleska@oen.siemens.de]

Hi PCIers,

the spec requires the target to complete the first data phase (within 16 
clocks if the host bridge is not snooping and) within 32 clocks from the 
assertion of FRAME# (with snooping). However it is not clear to me if the 
clock at which FRAME# is asserted counts as the first clock, Figure I,  or 
if counting begins at the clock after FRAME# was asserted, as shown in 
Figure II.



Figure I:
          1   2   3   4   5   6               30  31  32  33
          _   _   _   _   _   _               _   _   _   _    
CLK:    _| |_| |_| |_| |_| |_| |_............| |_| |_| |_| |_|
        __     __________________............
FRAME#    |___|
        _________________________...........__________     ____
TRDY#                                                 |____|  
or STOP#



Figure II:
          0   1   2   3   4   5               30  31  32  33
          _   _   _   _   _   _               _   _   _   _    
CLK:    _| |_| |_| |_| |_| |_| |_............| |_| |_| |_| |_|
        __     __________________............
FRAME#    |___|
        _________________________...........__________     ____
TRDY#                                                 |____|  
or STOP#


Can anyone clarify whats the right way of counting? 

Any comments appreciated,
-------------------------------------------------
Pavel Peleska		Tel: ++49 89 722-41253
Siemens AG			Fax: ++49 89 722-28502
SN EBG 11
Hofmannstr. 51
81359 Munich		Pavel.Peleska@oen.siemens.de
Germany
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