AMCC 5933 help needed

["Mark D. Schilling" <mdschi@most.fw.hac.com>]

Hello PCI Experts,

I have a problem with the 5933 PCI Controller. 
I am not getting a PTATN# assertion when I attempt to access BADR1.
I have the 5933 configured as follows:

BADR0 64 Bytes I/O 
BADR1 256 Bytes I/O 32 bits Pass thru width
The BIOS sets them up as follows.
BADR0 resides at FF00
BADR1 resides at F800

I can access BADR0 just fine. ( Reads and writes).
But accesses to BADR1 do not work. I read back only zeros.

According to AMCC , accesses to BADR1 should result in a PTATN# signal being
asserted.But it does not.

Lookin at the PCI bus cycle specifics:

When I do single read and write accesses.
I/O Read cycles look identical between BADR0 and BADR1 read requests.
I/O Write cycles however differ in the fact that the STOP# signal is
asserted during BADR0 accesses but not during BADR1 accesses. 
According to the AMMC manual figure 7.5 STOP# should be asserted becasue the
S5933 supports fast zero wait state write cycles but does not support burst
writes to operation registers.

What would cause the STOP# signal to not be asserted during a BADR1 access?

Any ideas out there?

Mark
----------------------------------
Mark D. Schilling               Phone: (219) 429-4239   Fax: (219) 429-5799
Hughes Defense Communications                           Mail Stop: 15-22
1010 Production Road, Fort Wayne, IN 46808-4106
Email: mdschi@most.fw.hac.com
Sxe