re: <none>

[YVazir@corp.adaptec.com]

Form: Reply
Header: Adaptec
Text: (8 lines follow)
As you said per PCI 2.0 specification the P2P bridges must flush their write 
post data before completing a downstream READ transaction.  Therefore, the 
CPU (Host) bridge should let the P2P complete its transaction.  About two 
years some host bridges did exactly what you suggest.  However, we convinced 
them that the proper operation per PCI Spec is to let the P2P complete its 
Posted transaction. Since then they all have revised their silicon to avoid 
this deadlock.  Disabling Write posting in P2P severely limits performance 
of downstream devices and in affect is a no-solution.
Original text: (52 lines follow)
From pci-sig-request@znyx.com, on 5/2/97 8:39 AM:
Subject: Transaction ordering

Dear Collegues,

assume a, e.g. Pentium-to-PCI, host bridge implementing a simple 
arbitration of the master and target data path, with the master path 
(processor to PCI) having a higher priority than the target path (PCI to 
main memory). The target in the host bridge has an address latch and a data 
FIFO, so only one write transaction can be posted to the host bridge (can 
complete on the PCI bus) before the data is actually written to main 
memory. Following write transactions will be retried by the host bridge 
until the data is written to main memory. If the processor initiates a 
master PCI transaction, i.e. a processor transaction to the PCI is started, 
the Target in the host bridge cannot access the main memory anymore, 
neither for reads nor for writes, until the master (processor) transaction 
has completed. This will obviously lead to a deadlock condition if the 
master (Processor) reads from a device behind a PCI-to-PCI Bridge (with 
write posting enabled) in case the PCI-to-PCI Bridge contains more than one 
posted write from the accessed device, as the P2P Bridge is required to 
flush its buffers before completing the read transaction (as per PCI Spec., 
Chapter 3.2.5, Transaction Ordering). However this configuration can be 
excluded.

Does anyone see another potential deadlock if:
- All devices that will be accessed by the host bridge (processor), e.g. 
Ethernet Controller, SCSI Ctrl etc., are on the primary PCI Bus, i.e. there 
is no P2P bridge in the system

- or if there is a P2P bridge, the P2P bridge is configured not to support 
write posting, i.e. P2P briges? write buffers will never have to be 
flushed?


Does anyone know peripherial controller devices, like the above mentioned 
SCSI and Ethernet etc., that will flush their (master) write buffers before 
servicing a read as a target?

How does a typical controller device behave?

Any comments very appreciated.

------------------------------------------------
Pavel Peleska   Tel: ++49 89 722-41253
Siemens AG      Fax: ++49 89 722-28502
SN EBG 11
Hofmannstr. 51
81359 Munich	   Pavel.Peleska@oen.siemens.de
Germany
------------------------------------------------


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