Re: 3v3 signaling, noise margin and universal card.

[Andy Ingraham <ingraham@wrksys.ENET.dec.com>]

A few weeks ago, Thierry Bassett (basset@csti.fr) asked some
questions that apparently went unanswered, about 3.3V and Universal
PCI adapters.  Maybe nobody answered because so few people are
actually using 3.3V signaling; but there are several Universal
PCI adapters on the market.

Thierry concluded that they couldn't build a Universal adapter
board.  While his reasoning makes sense, I think their fears may
be exaggerated.

Thierry first pointed out the fact that the noise margin in the
3.3V signaling case is reduced when sending and receiving chips
use independent 3.3V power supplies.  This is true.  (I don't know
if that was considered when drawing up the PCI Spec.)

Let me point out, however, that the minimum noise margins in the
3.3V PCI signaling environment are 0.90V and 0.54V for the high and
low states, respectively, when using separate power supplies.

That looks pretty good to me, especially when you consider that the
noise margins in the 5V PCI signaling case are only 0.40V and 0.25V. 
So, in the 3.3V case, the voltage swing is smaller, yet the noise
margin is bigger.  This sounds like an improvement; doesn't it?

So I wonder ... what's the problem with having a 3.3V regulator on
the Universal adapter board, in a 3.3V PCI system?  It seems like
you should be able to do it.

Regards,
Andy Ingraham



> Hi,
> 
> i have a question about noise margin in 3V3 signaling.
> 
> I suppose two 3V3 components on the PCI bus, powered or not from
>  the same 3V3 supply.
> 
> Standard configuration: 
> ----------------------
> The emitter and the receiver are powered from the same 3.3V supply.
> The lowest supply can be 3.0V.
> 
> 3.0V                                              3.0V
>     +-----+ out                       in  +-------+
>     |     |------------------------------>|       |
>     |     |                               |       |
>     +-----+                               +-------+
>       (VoH)min = 0.9*Vcc         (ViH)min = 0.5*Vcc
>                = 2.7V	                  = 1.5V
> 
> => the noise margin is 2.7 - 1.5 = 1.2V.
> 
> 
> Worst configuration: 
> --------------------
> The emitter and the receiver are not powered from the same 3.3V supply.
> The lowest supply can be 3.0V, and the highest one 3.6V.
> 
> 
> 3.0V                                              3.6V
>     +-----+ out                       in  +-------+
>     |     |------------------------------>|       |
>     |     |                               |       |
>     +-----+                               +-------+
>       (VoH)min = 0.9*Vcc         (ViH)min = 0.5*Vcc
>                = 2.7V	                  = 1.8V
> 
> In this case, the  noise margin is reduced to 0.9V.
> 
> 
> 
> Question:
> ---------
> Is this reduced noise margin acceptable? (i think so).
> Are these 1.2V an absolute minimum on which the PCI 2.1 specification
> is built (I don't think so) ?
> If so, it would imply that you must powered the emitter and the receiver
> (their IO buffers at least) from the same 3V3 power. This seems not viable 
> to me.
> 
> Any comments ? 
> 
> 		Thierry Basset.


> Hi PCI experts,
> 
> i'm currently designing an 155 Mbit/s ATM PCI board.
> I am wondering if i can design an universal board ?
> 
> I will use a proprietary 3V3 asic with 5V tolerant io for 
> the PCI interface.
> 
> With this component, i can work in 5V signaling without
> problem. 
> 
> If i want to use my asic in a 3v3 signaling environment,
> according to my signal integrity expert, i'm required
> to supply my component with the 3v3 PCI rail.
> 	He says so, because the noise margin will be
> reduced if two 3v3 signaling components are not supplied
> with the same 3v3 power. (on page 128 of the 2.1 PCI spec.
> i can effectively read that Vih is not an absolute value,
> it's 50% of Vcc.)
> 
> If he is rigth, i am required to supply my asic with the
> 3V3 PCI rail. It's not possible for me: 5V motherboard 
> are not required to supply 3v3.
> 
> So, i cannot design an universal board.
> 
> I will design:
> 1) first a 5V signaling board (with an on board regulator to 
> supply my 3v3 components.)
> 2) later a 3v3 signaling board (with my PCI interface asic
> supplied by the 3v3 PCI power rail).
> 
> 
> Any comments would be appreciated,
> 
> thanks in advance.
> 
> 			Thierry Basset
mXE