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PCI Local Bus Version 2.2



---------------------------- Forwarded with Changes ---------------------------
From: Warren Questo
Date: 5/13/97 12:13PM
To: Warren Questo
Subject: PCI Local Bus Version 2.2
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To all PCI SIG Developers,

As many of the PCI SIG members know, there are several changes to the PCI 
Local bus specification forthcoming.  As a result of these changes, the PCI 
Local Bus Specification revision 2.1 is going to be revised to 2.2.
 
The 2.2 revision will add support for new capabilities (Hot Plug and Power 
Management) along with several other changes.  As none of the revisions will 
result in a change to the PCI bus architecture, the revision would normally be a
2.11, but because some of these changes must be implemented to remain fully PCI 
compliant, the Steering Committee decided to label the revision as 2.2. 

Below is a list of ECNs that have cleared Work Group/Steering Committee 
review, but still need to be reviewed by the PCI SIG membership.  These are 
all targeted for incorporation into the local bus specification version 
2.2.  ECNs marked with an * are posted on the PCI SIG webpage in the members 
section and are being distributed as hard copy to all PCI SIG members for their 
review.


* PME#            Describes wake up function assigns (unused) pin on        
                  PCI bus to support Power Management
* Sub ID          Subvendor configuration space changed from optionally     
                  configurable to required for most classes of devices
* VPD             Provides alternate access method to vital product data    
                  and makes it a required feature
* Mech ECN#1      Bracket Mounting for EMI reduction
* Mech ECN#2      Increase size of I/O window-enable new connectors
* Mech ECN#3      I/O connector volume-enable add-in card insertion
* Mech ECN#4      Riser Connector-add-in card interface
* Mech ECN#5      Tighten Critical Tolerance-improve addin card seating
* Mech ECN#6      Mech Errata (wrong datum ref), Components free areas
* PMW             Improved (clarified) way to handle posted memory writes   
                  to prevent situations which may lead to a deadlock
Tprop             Clarifies measurement and determination of Tprop times    
                  for 33/ 66MHz
RST# Timing       RST# timing requirements to support Hot Plug and Power   
                  Management


These ECNs will follow the change process that has several steps (outlined 
below). This process fully involves over 600 members, all of which have the 
right (privilege of membership) to review and make comment on their 
specification. Somewhat cumbersome, but we achieve industry wide buy-in, 
awareness, and most importantly, full compliance with new changes that will 
effect millions of platforms and 10's of millions of add in devices in just 
a couple of years.

All of the ECNs to the PCI specification are at step 5 or 6 (exception is 
Expanded Capabilities already approved, which is at step 8).  It is planned 
to have a 2.2 revision in the 2 half of this year providing there are no 
major concerns encountered during the final review steps.

1. ECR (engineering change request) submitted in writing to the Chairman of 
   the Steering Committee
2. Steering Committee member(s) review ECR
3. If approved, the ECR is sent to an existing Work Group or a new Working  
   Committee is formed if the change is deemed to be of significant scope 
4. Working Committee develops the specification, details the changes, cross 
   checks for compliance with other working committees, and writes an (ECN) 
   Engineering Change Notice
5. ECN presented to Steering Committee for approval
6. ECN sent to the entire active PCI SIG membership for 30 day review
7. Written comments (if any) are summarized for the Steering Committee by   
   the Chairman  
8. Steering Committee reviews comments and votes (2/3 required to pass) for 
   approval
9. If approved, the specification changes are made and revised documents    
   are sent to all members.

Warren Questo
Chairman PCI SIG
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