Re: Memory prefetch

[Bruce Young <youngbru@pionet.net>]

You seem to imply that Intel chipsets do not allow a master to burst
read from host memory. This is not correct. Most (if not all) Intel
chipsets allow a burst read of at least a cache line in length
(aleviating the "cache coherency" problem alluded to) but several,
including "Natoma" (440FX) allow longer length bursts up to a 4k page
boundary. The 440FX does require you to use the read multiple command to
achieve the longest possible burst. In fact it may require read line or
multiple to burst more than 2 DWORDS -- I can't remember right now --
but I am sure that everyone out there is now using the enhanced read
commands after all the discussion it has received here :-). 

You are right that it is not possible to initiate a read burst of a PCI
device from the CPU and that there are no DMA engines for bursting data
from memory to a PCI device in any x86 chipset I am aware of. The i960
RP does have DMA engines to do this but it would be pretty hard to build
a Win95 machine out of it!!!!

-Bruce Young
Gateway 2000
on the net I speak for myself, not Gateway (or Intel)



Dave New wrote:

> ..........
> Also, bursting data *from* the host memory *to* a PCI initiater is
> generally not supported by most host chipsets.  Intel cites
> host memory cache coherency complications as the reason for
> not supporting this.  ........
> 
> -- DaveN
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