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Re: Memory prefetch
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Memory prefetch
- From: Dave New <den@aisinc.com>
- Date: Mon, 09 Jun 1997 11:28:09 -0400
- Cc: Mailing List Recipients <pci-sig@znyx.com>
- Organization: Applied Intelligent Systems
- References: <339A4B9F.14F2@pionet.net>
- Resent-Date: Mon, 09 Jun 1997 11:28:09 -0400
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"Q8iw-1.0.R44.bN3dp"@dart>
- Resent-Sender: pci-sig-request@znyx.com
- Sender: den@aisinc.com
Bruce Young wrote:
>
> You seem to imply that Intel chipsets do not allow a master to burst
> read from host memory. This is not correct. Most (if not all) Intel
> chipsets allow a burst read of at least a cache line in length
> (aleviating the "cache coherency" problem alluded to) but several,
> including "Natoma" (440FX) allow longer length bursts up to a 4k page
> boundary. The 440FX does require you to use the read multiple command to
> achieve the longest possible burst. In fact it may require read line or
> multiple to burst more than 2 DWORDS -- I can't remember right now --
> but I am sure that everyone out there is now using the enhanced read
> commands after all the discussion it has received here :-).
>
I recall the read line/multiple thread from some time ago, but missed
the information that the current crop of Intel chipsets supported
burst reads from a PCI initiator of one sort or another, apparently
through the read line/multiple mechanism(s). Thanks for pointing
this out, Bruce. My experience with the 440FX is rather recent,
so I'm just still finding out things about that chipset.
> You are right that it is not possible to initiate a read burst of a PCI
> device from the CPU and that there are no DMA engines for bursting data
> from memory to a PCI device in any x86 chipset I am aware of. The i960
> RP does have DMA engines to do this but it would be pretty hard to build
> a Win95 machine out of it!!!!
>
I'd like to use the RP on a plug-in board, but the non-PCI 2.1 clock
compliancy issue, and the lack of support for running an asynchronous
secondary PCI bus clock has stopped me. Apparently it is OK for
build-in solutions, where the system designer has control over the
system bus clock design. I've also been made to understand that
a redesign of the RP core (from dynamic to static) would be necessary
(and not very probable) to eliminate the clock issues. Too bad.
We've used the C-core for years now, and so I can say that we *know*
the i960 8-).
Cheers,
-- DaveN
° d T