PCI Question

[DMitteer@aol.com]

Hi All,

I am somewhat confused about how to interpret the PCI 2.1 spec. as it applies
to Target Inititial Latency (Section 3.5.1.1 in the spec.)

The spec states:
"Target initial latency is the number of clocks from the assertion of FRAME#
to
the assertion of TRDY# which completes the initial data phase, or to the 
assertion of STOP# in the Retry and Target-Abort cases."

In the next paragraph the spec. also states:
"All targets are required to complete the initial data phase of a transaction
(read or write) within 16 clocks from the assertion of FRAME#."

The question is when to start "counting" the 16 clocks:  That is, is it
the cycle AFTER FRAME# is asserted as follows:

                 0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18
CLK           ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^
FRAME#     ---\__/------------------------------------------------------
IRDY#      ------\_______________________________________________/------
TRDY#/STOP#---------------------------------------------------\__/------


Or does the assertion of FRAME# count as cycle #1 as follows:

              0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19
CLK           ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^
FRAME#     ---\__/------------------------------------------------------
IRDY#      ------\____________________________________________/---------
TRDY#/STOP#------------------------------------------------\__/---------

In the above diagrams, the ^ means the rising edge of the PCI clock.

Can anyone shed some light......


Thanks in advance.


Dave Mitteer
µl\