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D1/2 PM States
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: D1/2 PM States
- From: Leonid Smolyansky <leonid@msil.sps.mot.com>
- Date: Tue, 17 Jun 1997 19:26:51 +0300 (GMT+0300)
- Resent-Date: Tue, 17 Jun 1997 19:26:51 +0300 (GMT+0300)
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Hello,
In the PCI Bus PM Spec, Rev.1.0, I did not find explicit definition of
REQ# and INTx# signals behavior during D1/2 Power Management states.
Should these signals be deasserted in D1/2 states if they were asserted
prior in D0 state?
Thanks for clarification.
Best regards
Leonid Smolyansky
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