[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

re: D1/2 PM States


>  From: Leonid Smolyansky <leonid@msil.sps.mot.com>, on 6/17/97 11:51 AM:
>  Hello,
>  
>  In the PCI Bus PM Spec, Rev.1.0, I did not find explicit definition of
>  REQ# and INTx# signals behavior during D1/2 Power Management states.
>  Should these signals be deasserted in D1/2 states if they were asserted
>  prior in D0 state?
>  
>  Thanks for clarification.
>  
>  Best regards
>  
>          Leonid Smolyansky
>          _________________       
>          
>          E-mail:        leonid@msil.sps.mot.com
>          Tel: 972-9-9522258  Fax: 972-9-9522740
> 
When in the D1, D2 and D3hot states, PCI-PM devices should maintain signal
levels commensurate with an Idle Bus state defined within the PCI 2.1 spec.
Basically, REQ# and IRQ# are tristated.
The PCI-PM 1.0 specification precludes functions from generating any bus
activity (other than PME#) when in D1, D2 or D3 power states.

Thanks,
Brian Belmont		Voice: 	972.997.6021
Texas Instruments	Fax:	972.997.6301
PC Systems Lab		MsgID:	BVB1
					Internet: bbelmont@ti.com

Ãl[