Re[2]: BIOS interrupt configuration

[Brad W Hosler <Brad_W_Hosler@ccm.jf.intel.com>]

Don't be confused by the Intel chipset supporting four routable interrupt 
lines (named PIRQA, PIRQB, PIRQC, PIRQD) and the interrupt pins on a PCI 
connector (INTA, INTB, INTC, INTD).  Most motherboards connect the INTA 
pin of each connector to different PIRQx lines so that there does not have 
to be interrupt sharing.  For instance, the table below shows a sample 
routing of the INTx pins on each connector to the PIRQx inputs on the 
Intel chipset.

           Slot1      Slot2     Slot3     Slot4
INTA       PIRQA      PIRQB     PIRQC     PIRQD
INTB       PIRQB      PIRQC     PIRQD     PIRQA
INTC       PIRQC      PIRQD     PIRQA     PIRQB
INTD       PIRQD      PIRQA     PIRQB     PIRQC

Using this example, a device in slot3 that uses an interrupt (INTA) will 
actually be connected to PIRQC on the Intel chipset, and the value at 
offset 0x62 in the chipset config space will indicate which IRQ the device 
is actually connected to.  THis value should correspond to the value that 
is written into the device's config space at offset 0x3C.

Note that the above routing table is just an example.  Most motherboards 
will do something similar but not exactly the same.

Brad



Sounds like the BIOS does not know how the board is tracked.
     
 ----------
From:      pci-sig-request[SMTP:pci-sig-request@znyx.com] 
Sent:      18 June 1997 14:12
To:      Mailing List Recipients
Subject:      BIOS interrupt configuration
     
Hello,
     
We have some troubles related to PCI interrupts on our board. On our 
board
we have the Intel Triton 82430HX and 82371 PIIX3 controllers.This board 
is
running a BIOS designed for this chipset. On this board we have  PCI 
devices
which have one interrupt Int A. For some devices, this interrupt is 
cabled
on our PCI bus on another line, int D for exemple, this seems to be 
authorized by the PCI revision 2.1, see page 14.
During the configuration stage, the BIOS configures the PIIX3 to route 
the
PCI interrupts. Thanks to the PCI analyser I can see what is written in 
the
PIIX3 controller ( register PIRQC[A:D] offset 60-63h in the config space 
function 0) . So
int A is routed to irq 11
int B is routed to irq  10
int C is routed to irq  4
int D is routed to irq  9
     
I also have a look at the header of my PCI devices. One of the device 
which
int A is cabled to int A of the bus should have at offset 3C of the 
configuration space the value 11 for its interrupt line, to be in 
accordance
with the programmation of the PIIX3. But the value written and read is 
10,
as if its interrupt pin was B.
An other device which intA is cabled to int D has 11 as interrupt line, I
     
think it should be 9 according to the PIIX3.
     
     
When we use the routing facility described on page 14 of the spec, that 
is
int A of one device cabled to int D for instance, how can the BIOS know 
this
as, in the configuration header, the interrupt pin is A. In our case it 
is
strange because if the BIOS relies on the interrupt pin, it should write 
11
and not 10 in the interrupt line for the device with intA connected to 
intA
of the bus. So the fact that the interrupts can be re-routed (intA 
connected
to intD.....) may be a problem but not the only one.
     
So, if the OS reads the configuration space of each PCI device, it does 
not
get the right interrupt line and can not run.It must know the hardware 
configuration of the board and read the PIIX3 register to get the 
interrupt
line. This is not what is usually done by most OS (linux for example). So
     
what is wrong ?
Is it the BIOS or is it the board design ?
     
Any help would be appreciated.
     
Thank you
     
Anne

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