Re[2]: 440FX PCI CHIPSET performance

["Kim Olsen" <kolsen@nfsrv.avionics.itt.com>]

     Dave,
     
     Is you PPRO system inserting the wait states at or before the host?
     
     If the logic that aligns the data between the 32-bit and 64-bit 
     interfaces is not fast enough, the wait states would be inserted for 
     this reason.
     
     Kim


______________________________ Reply Separator _________________________________
Subject: Re: 440FX PCI CHIPSET performance
Author:  pci-sig-request@znyx.com at ccminet
Date:    6/26/97 10:10 AM


Graeme Gill wrote:
> 
> I have tested two Pentium Pro based systems that use the 440FX chipset, 
> and had very disappointing results.
> 
I've had a similar experience, but with using the 440FX to master 
transfers to a PCI target.  By executing a x86 REP STOSD instruction 
on earlier 166MHz Pentium machines with Triton II bridges,
the host bridge would combine the writes and burst to the PCI target 
with a series of zero-wait state 32-bit data phases.  The host would 
break the bursts on host cache line boundaries, though.
     
Moving to a 200 MHz PPro single CPU EDO machine, running the same 
instruction sequence produces an arbitrarily long burst, but
it actually wastes a lot of PCI bus bandwidth, because the host 
bridge is inserting wait states (deasserting IRDY) about 50-75% 
of the time during the multiple data phase burst.  The result 
is overall poorer throughput, while the PCI bus is essentially 
saturated by this activity.  I can't believe that a 200 MHz
(66 MHz local bus) 64-bit PPro can't keep a host bridge that 
is talking to a 33 MHz 32-bit PCI bus busy.
     
It boggles the imagination... 8-).
     
Cheers,
     
-- DaveN
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