Electrical State of bus signals during D3cold/B3

[Jeff Lee <jlee@atlanta.nsc.com>]

I am looking for a clarification on certain aspects of the PCI Power
Management bus B3 state and function D3cold state.

Background
----------
The PCI Bus Power Management Spec v1.0 defines D3cold as a state in
which power to a specific PCI bus segment is removed (PCI bus state B3).
PCI devices located on this segment may optionally support PME while in
the D3cold state. Special considerations are detailed for the device pin
connected to the PMEN signal, and the use of auxiliary power to maintain
PME context.

Spec Ambiguity
--------------
The issue which is not clearly articulated in the above spec is the
electrical state of the PCI bus signals which are connected to the
device in the D3cold state.

Questions
---------
1. Is the D3cold state only entered when the bus moves to state B3?

2. Is it safe to assume that the PCI bus signals are in a high-impedance
state when a device is placed in a D3cold state? The spec calls for
"backdrive" protection on the PMEn signal, but makes no mention for
special considerations on the other bus signals.  

3. Is anyone implementing (or know of someone else implementing) slot
specific power management, under which a single PCI slot is powered down
(VCC removed), but the reset of the bus remains active (not in a
high-impedance state). Would such an implementation imply the need for
"backdrive" protection on all bus signals.



-- 
ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
   ------   __e       Jeff Lee, Principal Engineer (jlee@nsc.com)
-------   _`\<,_      National Semiconductor, LAN Division
   ----  (*)/ (*)     500 Pinnacle Court, Suite 525, Norcross, GA 30071
~~~~~~~~~~~~~~~~~~~   ph: 770-903-1851  fax: 770-903-1827
ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

Õ°Ÿ