RE: 440FX PCI CHIPSET performance

[Graeme Gill <graeme@digideas.com.au>]

Dave Feng <dfeng@iced.com> wrote:

> If you are using the AMCC S5933, there is an undocumented bit that
> enables the PCI read line/multiple cycle.  If you don't use this
> explicitly, depending on the motherboard chipset, you may or may not be
> bursting more than a cache line.

No, I'm using the 9060SD, and already using MRM and MWI.

> My experience is the same as you guys with the 440FX.  I was getting
> sustain of 55(112 peak) for writes and 30(60 peak) for reads.  On the
> 430TX I was getting 55(same) for writes but 64(> 2x) for reads.

The problem I explained is that I haven't been able to get anywhere
near 55 Mb/sec writes or 30 Mb/sec reads sustained using the 440FX.
The best I have seen sustained is less than 10 Mb/sec.

>  Once I enabled the hidden bit the 440FX behaved much like the 430TX.
> So(drum roll please), the bit you need to enable is bit 15 of the MCSR.

I can't find any register in the 440FX called MCSR. 

Graeme Gill

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