Re: 440FX PCI CHIPSET performance

[Dave New <den@aisinc.com>]

Kim Olsen wrote:
> 
>      Dave,
> 
>      Is you PPRO system inserting the wait states at or before the host?
> 
I'm not sure what you mean by this question.

>      If the logic that aligns the data between the 32-bit and 64-bit
>      interfaces is not fast enough, the wait states would be inserted for
>      this reason.
> 

The 440FX is performing the 64-to32-bit interface, as far as I know.
I haven't measured what's happening on the 64-bit CPU-local side of
the host bridge chipset, although I have imagined (8-)) that it isn't
the CPU that is holding up the process -- rather it would seem to be
the bridge, but it's just a guess on my part.  The result, though,
is the same -- on a 200 MHz PPRO system running the 440FX chipset, the
host-to-PCI throughput is not as good as a 166 MHZ Pentium running
a Triton bridge.

Seems counterintuitive.  Maybe the PPRO is keeping the L2 cache busy
pre-fetching instructions to keep the superscaler units busy, thus
clogging up the CPU's bus interface unit for sending things off
to external memory locations.  Gotta' keep that 200 MHz CPU fed
somehow...

Cheers,

-- DaveN

×p
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