Re: 440FX PCI CHIPSET performance

[Graeme Gill <graeme@digideas.com.au>]

Bruce Young wrote:
> You don't say but I assume that you are performing reads here. I will
> also assume that you double-checked to be sure that you are using the
> MRM command.

Checked, double checked, checked again. Made sure it wasn't the test
gear causing the problem.

> Given that I am a little bit confused about what is going
> on. The first read is is treated as a delayed read request. Then when
> the master comes back it is treated as a delayed read completion
> although it is an awfully long latency for the read (31+17+idle time or
> ~1.5 us). This would seem to imply that the P6 bus if VERY busy and
> there were several bus transactions queued up in front of it.
> 
> It also is a little bit surprising that only one cache line of data is
> delivered. It should always deliver at least 2 cache lines of data when
> a MRM command is used. This actually sounds more like the behavior of a
> standard read command.

I can confirm that all the cycles above are transfering 8 32 bit words.

For interest I switched to using the MR command, and yes, the sequence
resulting looks very very similar. When using MR, I didn't catch it
using any bursts though. When using MRM or MRL it does bursts up
to the point when this behaviour starts, and some wait stated bursts
during this behavour.

> My first cut at this is that the P6 bus is much more than "slightly"
> busy when this occurs. But this still does not explain why only 32 bytes
> are delivered. Any of you current Intel guys want to take a cut at this
> one?

Nothing out of the ordinary triggers this behavour. Windows NT is basically
idle during this test.

Graeme Gill.


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