I don't understand exactly which is the errata you are talking about.
I used S5933QB in the bus master
mode, asserting and deasserting it's bus master enable pins from the
add-on side. I was first afraid that
according to the errata, the last retried long word from the FIFO(currently
in holding register) would get
lost during a data transfer from the add-on side to the PCI bus in
5933. This could happen only if we use
the add-on to PCI FIFO empty signal to indicate to the add-on side
hardware to deassert the bus master
enable signal. But in my case the add-on side 25MHz uP responded quite
slow(interrupt driven and hence
kernel dependent too!!) to deassert the bus master enable signal,
any retry would have got finished by
that time. So I didn't face a problem during the last dword retries!
So it all depends on the speed of the
add-on side hardware. I feel that this is because, according to the
PCI Specs., the retry should get
completed with in 16 clock cycles. But your problem could be different
so I don't know whether this was of any help.
regards
-Jasper
--
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* * * *
*
*
* Jasper Balraj
*
* Senior Engineer - Hardware
*
* Wipro Ltd.,
*
* (Wipro Infotech Group
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* Global R&D Division)
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* 37 Castle Street, Ashok Nagar, Tel
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Fax : 91-80-5576032
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