PCI Burst Performance

[Gary Stein <gstein@sntc.com>]

There has been much previous discussion about PCI master burst
performance from system memory on various chip sets, but nothing in the
archives that correlates to what I've found.  I'm posting this to assist
others that may have struggled with this, and perhaps someone can share
some insight into the history or motivations behind the situation.  I
welcome any comments or observations.

In some 430HX platforms, I have observed all read bursts being
disconnected at 8 dwords (32 bytes) by the host bridge, even when the
issued command is Read Line or Read Multiple.  This performance is
contrary to the 82439HX spec, which talks of the 22 Dword PCI-DRAM read
prefetch buffer, 112MB/sec read performance, and postings to this group
talking of 4K bursts.  In researching this issue, I stumbled across this
posting in Intel's PCISet newsgroup area:

:> PCI Streaming Bit (bit 1 $50)

:>The 82437FX chipset had a bit in register $50 (bit 1) that is called
:>'PCI STREAMING'. If set to 0 then streaming is enabled. If set to 1 it
:>is disabled. If this bit is set to 1 it appears (via a PCI analyzer)
:>that only 8 DWords are allowed to occur in a burst DMA to system
memory
:>before the burst transfer is stopped via the PCI #STOP signal. This is
:>being caused by the 82437FX chip. If this bit is set to 0 then the
full
:>burst will occur uninterrupted.
:>
:>Actually, I don't have any systems with an FX chipset, but I do have
:>several with HX and VX chipsets. I observed this behavior on these
:>systems. The documentation for the HX and VX chipsets refers to bit 1
:>of $50 as a 'reserved' bit, whereas the FX docs refer to it as the
'PCI
:>Streaming bit'. All of the docs say that the default value for this
:>register is $00. The docs also say that ANY bit described as reserved
:>should NEVER be altered. However, on some of my systems this bit is
set
:>after boot up, and on others it is not set. 
:>
:>Although the bit is described as reserved for the HX and VX (and TX)
:>chipsets, it appears that it does have some affect - most probably the
:>same affect as was originally intended in the FX chipset. I see no
:>reason for this bit to ever be set! Intel undoubtedly agrees with me
:>because they now refer to it as reserved and clearly intend for it to
:>be
:>set to $00 (it is set to $00 on a hardware reset).
:>
:>So, my questions are...
:>
:>Who is setting this bit?
:>Why is this bit being set?
:>All of my machines have AWARD BIOSes, but they set it differently.
:>What is the historic signifigance of this bit?
:>
:>The simple solution is to have my device driver reset this bit. This
is
:>not technically 'legal', but I gotta do what I gotta do. I would sleep
:>better if I understood what this bit was intended for.
:>

The post seems right on the mark.  On my HX machine (Intel Advanced/ML
(Marl) mombo), bit 1 at config offset $50 is set by the BIOS, and I get
32 byte read bursts.  If I clear the bit after booting, long bursts are
obtained.  The post saw this with an AWARD BIOS, I'm using the latest
AMI 1.00.09DB05.  I have other machines where this bit is cleared.
Interestingly, this mythical reserved bit even seems to exist in the
440LX, where one can write/read it at will, but I have not verified any
system effects.

Bottom Line is that there are some buggy BIOS's out there that do not
configure chipsets properly.  If you are seeing short PCI bursts, check
bit 1 @ offset 50 !!


Gary Stein                                               
Senior Hardware Engineer                         gstein@sntc.com

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