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RE: Re: PCI Signal Loading
- To: Mailing List Recipients <firstname.lastname@example.org>
- Subject: RE: Re: PCI Signal Loading
- From: Andrew Ingraham <Andrew.Ingraham@digital.com>
- Date: Tue, 10 Feb 1998 16:09:45 -0500
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- Resent-Date: Tue, 10 Feb 1998 14:48:52 -0800
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> The way I understand the loading problem is that the capacitance of
> the finger connectors on the card edge is high enough to generate
> another capacitive load. By my understanding, and this was mentioned
> specifically at the PCI Plus technical seminar last spring, it is this
> that adds the load, since it is the capacitive not resistive load that
> causes the problems.
I don't know what you mean by resistive load. PCI is not a terminated
environment, and steady-state currents are minimal.
A mated PCI connector pin is about 1-3 pF and 6-8 nH, according to old
measurements and vendor data. If you consider these as distributed as
opposed to lumped, or if the connector length is insignificant at
frequencies of interest, then this is about the same as a short (<200ps)
length of roughly 70 ohm transmission line. As an element in series
with a signal trace, this doesn't seem like enough of a discontinuity
itself to be considered a second capacitive load.
The 1.5" of trace on the card, at 2-3 pF per inch, represents another 4
pF or so; more than the connector itself.
> Since the compact PCI uses a pin connector, the capacitance imparted
> is less. I have not looked into the capacitance of the finger
> connectors, since that is not part of my end product, but the
> capacitance in a pin connector is usually in the area of 1pF or 2pF,
> which is 1/10 the typical capacitance of a semiconductor input. This
> is part of what allows CPCI to have upto 8 slots on a backplane
> without a bridge. That along with a specific 65 ohm trace impedance
> vs. 50 - 100 ohm range for standard PCI are the main differences in
> the two formats.
One of the primary electrical features of CompactPCI, is the termination
added to every bussed signal. Each signal has a 10 ohm series (stub
termination) resistor on each card. I believe that is the main reason
why CompactPCI can have 8 slots in a backplane.
A "specific 65 ohm trace impedance" is wishful thinking. 55-75 ohms
(what one can expect from manufacturing tolerances) is narrower than
60-100 ohms. But trace impedance has a relatively minor effect here.
Since this is a stub, the higher the impedance (lower capacitance), the