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Adress/Data Stepping


Does anyone have any experience with components using address/data stepping?
Although this is permitted by the specification, it is also "discouraged"
both for performance as well as timing reasons.

Specifically, I'm looking for feedback on timing problems.  e.g., If
a component is using continuous stepping, other components may have
problems when their input setup and hold is violated even though they should
not be sampling the signals being stepped.

I know that this *should* work based on the spec., what I need to know is
does anybody have any real experience either with designing a component that
uses this technique, or interfacing to a component that does.  Or, does
anyone see any other potential pitfalls that I may have missed?


Brian Sassone (brians@aureal.com)                Aureal Semiconductor
HW Design Manager, PC Products Group             4245 Technology Drive
510-252-4225                                     Fremont, California 94538