Re: Adress/Data Stepping

["T.Nakamura" <takashi_nakamura@yokogawa.co.jp>]

Dear Mr. Brian Sassone,

> Specifically, I'm looking for feedback on timing problems.  e.g., If
> a component is using continuous stepping, other components may have
> problems when their input setup and hold is violated even though they should
> not be sampling the signals being stepped.

Spec2.1, page83, section3.7.3, third paragraph:

  Stepping is only permitted on AD[31::00],AD[63::32],PAR,PAR64# and
  IDSEL pins, because they are always qualified by contrl signals.

I think C/BE[7::0]# is forgotten to be included.
Latching invalid values on these signals during continuous stepping
isn't harmful. These signals are not connected to inputs of a
state machine. In other words, you can't make a design in which
these signals are inputs of a state machine.

Are you worring about metastable?
When these signals are latched on the qualified cycle, metastable
is cancelled and latched values are stable.
Use only latched values on the qualified cycle.

Regards,
Takashi Nakamura
Yokogawa Electric Corporation