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RE: [Fwd: PCI Reset Question]
- To: Mailing List Recipients <email@example.com>
- Subject: RE: [Fwd: PCI Reset Question]
- From: Garnett Hamilton <ghamilton@CHRYSALIS-ITS.com>
- Date: Mon, 23 Feb 1998 18:15:09 -0500
- Cc: "'PCI SIG Mailing List'" <firstname.lastname@example.org>
- Resent-Date: Mon, 23 Feb 1998 15:25:26 -0800
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From a message that I saved a while back ...
There is no explicit specification on the CFG space ready time.
The PCI expansion device is not really given any specific readying
time after reset goes away. Their are allusions (very slight)
to this in section 2.2.1 (System Pins, RST#) and in
section 6.1 (Configuration Space Organization). So there is
no grace period given at all. The official setup time is 0 ns
after RST# deassertion.
In practice, you probably have a few milliseconds (as in less
than 100ms). 500-600ms is way to long. That's 1/2 a second. Many
BIOS will get to the PCI device scan way before 500ms. The motherboard
BIOS as a rule are getting faster and faster. Many BIOS are already
faster than 100ms, like in the 50ms range.
This problem will be greater in the near future. With the Microsoft
OnNow (MS implementation of ACPI) efforts currently active, some BIOS
will simply be cramming previous configuration values into devices
from a previous successful bootstrap. This process will be even
faster than the actions taken in typical BIOS today. People are
demonstrating machines today that go from standby off to running OS
in 5 seconds. That time is substantially the time to reload the
memory contents from a disk. The actual POST actions of the motherboard
BIOS are taking place in about 1-2 seconds. The time from RST#
deassertion to access of configuration space is extremely small in
these systems (as low as 10ms). Slightly longer for non-chipset
PCI devices (such as expansion cards).
If you are looking at loading a device with a slow serial ROM, then
parallelization is requirement for your next turn. If your device
does not come ready in 100ms, I would say you are looking at definite
failures in the next few years on many systems.
In terms of architecture, the Steering Committee should have already
looked at this, but probably has not yet. The spec really needs to
be changed to give some minimum value for device setup. I would not
count on more than 100ms though since market powers are at work to
make the actually required ready time smaller and smaller.
There is an ECN expected to be incorporated into version 2.2 that allows
for 2^25 clocks after RST# is deasserted and before config accesses
I hope this helps you out.
===================Safeguarding the Keys to Electronic Commerce
Garnett Hamilton Chrysalis-ITS, Inc.
Manager, Hardware Development 200-380 Hunt Club Rd
Tel.: 613-731-6788 ext 120 Ottawa ON K1C 1V1
Fax: 613-731-1013 http://www.chrysalis-its.com
> -----Original Message-----
> From: email@example.com [SMTP:firstname.lastname@example.org]
> Sent: Monday, 1998 February, 23 5:22 PM
> To: Mailing List Recipients
> Subject: [Fwd: PCI Reset Question]
> On the PCI bus, do you know how much time is spec'd from the time
> reset (PRST#) is deasserted until configuration cycles are started or
> are permitted?
> I can't seem to find it in the PCI Local Bus revision 2.1 spec.
> Best Regards,
> Joe Fockler
> Texas Instruments
> PCIbus Solutions Applications
> 8505 Forest Lane, MS 8709
> Dallas, TX 75243
> (972) 480-6064 phone
> (972) 480-6400 fax
> http://www.ti.com/sc/pci << Message: PCI Reset Question >>