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Re: snooping PCLK???
- To: Mailing List Recipients <email@example.com>
- Subject: Re: snooping PCLK???
- From: Charles Burnett <firstname.lastname@example.org>
- Date: Mon, 23 Feb 1998 16:49:43 MST
- In-Reply-To: <34F187B0.BFEF1569@ncube.com>; from "Greg Loxtercamp" at Feb 23, 98 2:29 pm
- Organization: Hewlett-Packard, Colorado Springs, CO
- Resent-Date: Mon, 23 Feb 1998 15:58:06 -0800
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> Date: Mon, 23 Feb 1998 14:29:04 +0000
> From: Greg Loxtercamp <email@example.com>
> Organization: nCUBE
> Subject: snooping PCLK???
> The problem I have is that we need to run some circuitry
> on the card from the 33MHz PCI clock. This circuitry has to be exactly
> syncronous with the PCI clock...not from another on-board oscillator. I
> know that it is illegal to put two loads on the clock, so what is the
> best way to handle this situation.
You could add a zero-delay clock buffer to your circuit. ICS makes such
a part (AV9170), along with Cypress (CY2308). This will give you
multiple outputs to drive your loads. These parts use a PLL, so you need
to be certain that your incoming clock signal is clean with a low amount
of jitter. Emperically, I have found that the CY2308 part tracks a
little better than the ICS part. (Your mileage may vary.) Keep in mind
that even with a "zero-delay" part, the timing will change slightly. You
will need to be certain this is within your design tolerance.
If you can not tolerate any bus timing changes, you could add a PCI-to-PCI
bridge chip to your board. The DEC 21152 has multiple bus clock outputs
for devices on the secondary bus.
Charles Burnett Internet: firstname.lastname@example.org
Hewlett-Packard Co. Voice: (719) 531-4230
Network Systems Test Division Voicemail: (719) 590-2000
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