Re: snooping PCLK???

[Charles Burnett <burnett@col.hp.com>]

> Date: Mon, 23 Feb 1998 14:29:04 +0000
> From: Greg Loxtercamp <gregl@ncube.com>
> Organization: nCUBE
> Subject: snooping PCLK???

> The problem I have is that we need to run some circuitry
> on the card from the 33MHz PCI clock.  This circuitry has to be exactly
> syncronous with the PCI clock...not from another on-board oscillator.  I
> know that it is illegal to put two loads on the clock, so what is the
> best way to handle this situation.

You could add a zero-delay clock buffer to your circuit.  ICS makes such
a part (AV9170), along with Cypress (CY2308).  This will give you
multiple outputs to drive your loads.  These parts use a PLL, so you need
to be certain that your incoming clock signal is clean with a low amount
of jitter.  Emperically, I have found that the CY2308 part tracks a
little better than the ICS part.  (Your mileage may vary.)  Keep in mind
that even with a "zero-delay" part, the timing will change slightly.  You
will need to be certain this is within your design tolerance.

If you can not tolerate any bus timing changes, you could add a PCI-to-PCI
bridge chip to your board.  The DEC 21152 has multiple bus clock outputs
for devices on the secondary bus.


Charles
--
Charles Burnett                               Internet:   burnett@col.hp.com
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