questions for PCI Bus V2.1

[oneyjs@samsung.co.kr]

Hi
I am developing the raster image processor board that can interface to PCI Bus on the Pentium II platform.
But, I have some questions for using the PCI Bus.
 
  1. For a case of memory burst access(more than hundreds of Kilo Bytes transfer) 
     the start address is driven on AD[31:0] during address phase.
     The start address is determined in the Base address register, but
     how is the last address determined?
  2. If the start address is 00100000h and the memory space is 4MB,		
     can the start address for memory burst access(more than hundreds of Kilo Bytes transfer)
     begin at any address within the memory space(00100000h~00500000h) ?

  3. Can the memory on the Add-In Card be cacheable when it serves as the master ?

  4. when the target memory burst accesses to the system memory(host memory) on the platform,
     does the host CPU take responsibility to transfer the data to/from system memory until the access completes ?
     If not, does Host/PCI Bridge ?

I look forword to your quick response!!!
Thanks
Best Regards

e-mail:oneyjs@samsung.co.kr