Re: SM Bus bridge, PIIX4

["John R Pierce" <pierce@hogranch.com>]

rmhurt asks...
>I have a need to know the serial numbers of DIMMs and of Intel
motherboards,
>but I have not found any sample code for programming the SM bus to get this
>information..  Does anyone out ther know how to do this and where the
sample
>code or specs are?  For example, the PIIX4 manual does not clearly show
>WHICH I/O ports the SMBUS is located at.  Why is Intel so obscure about
>this?  I need to write software to identify the presence of the smbus and
>its locations, and the same for infrared port, and USB.  While the books
>mention offset address, they do not mention ACTUAL address.  WHAT ARE the
>actual addresses of these devices IN PRACTICE?  I am sure all manufacturers
>follow Intel's lead so their stuff will be compatible.  Do you know where I
>can get the standard?
>
>At what SMBUS address do DIMMs reside, and at what SMBUS do intel
>motherboard serial numbers reside?  How can I get a list of typical
>addresses and what occupies them?  How can I get a source sample to keep
>from reinventing the wheel?

sure, the info on the SMbus reading is right there in the PIIX4 manual, you
just need to understand how to interpret it.  I dug that info up for someone
else once, let me look again...

The SMBus IO ports base register is located in PCI Configuration space on
the PIIX4.  So you will need to use whatever method of PCI Config space
reads suits your environment (bios calls for DOS apps), find the PIIX4's
device ID code [ah, on the intel AL440LX, its always bus 0, device 7]....
The SMB base address is stored at PIIX4 function 3, offset 0x90.  Then use
ReadConfigDword(busdevfunc, 0x90) to get the base IO address for the SM Bus
controller.  The SMB Controller itself is all 8 bit io ports, so access it
with IN and OUT instructions (or inp(), outp() in C).

Looks like you write a SM address to IO port base+4, then issue a command on
port base+2, then wait for status on port base+1, and read the data from
base+5 and +6 ... etc  (or data at base+7 for the block IO commands).
Sheesh, looks complex.  There also appear to be commands that can be issued
to other SMB devices.

See the PIIX4 Data Sheet (Intel document 290562-01), section 7.1.27 thru
7.1.32 for the config space registers, and section 7.3 for the IO registers.

Now, near as I can tell, the actual address space of devices on the SMbus is
purely up to the specific motherboard, and does not appear to be documented
in the end user documentation for anything I've seen.  Oh, searching
http://developer.intel.com for any references to 'SMBus' turns up
ftp://download.intel.com/ial/wfm/smi2c_10.pdf which is the SMB
Specification. This lists some fixed addresses on page 5 (Table 3) for
things like DIMMs, etc..  It also appears this stuff is part of ACPI, so you
might dig up THOSE specifications and follow thru.

-jrp