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pci power management !!
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: pci power management !!
- From: Suku Koonantavida <suku_koonantavida@phoenix.com>
- Date: Wed, 11 Mar 1998 19:02:03 -0800
- Organization: Phoenix Technologies Ltd.
- Resent-Date: Wed, 11 Mar 1998 20:34:09 -0800
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"x2aV33.0.rU.h1s1r"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
- Sender: suku@phoenix.com
* The PCI Bus Power Management Interface Specification Version 1.0,
Chapter 5 talks about PCI function power management states.
If the function is in state D3 and supports PME# generation, and
a bus segment reset (RST_N#) occurs the PME context have to be
maintained. If the function supports PME# generation from other
states like D1 or D2 and in case a bus segment reset(RST_N#) happens
when in these states is it required to maintain the PME context?
Spec. is not clear about this. Can someone clarify?
* How to differentiate a power-on-reset and bus segment reset ?