[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

pci power management !!

* The PCI Bus Power Management Interface Specification Version 1.0,
  Chapter 5 talks about PCI function power management states.
  If the function is in state D3 and supports PME# generation, and
  a bus segment reset (RST_N#) occurs the PME context have to be
  maintained. If the function supports PME# generation from other
  states like D1 or D2 and in case a bus segment reset(RST_N#) happens
  when in these states is it required to maintain the PME context?
  Spec. is not clear about this. Can someone clarify?

* How to differentiate a power-on-reset and bus segment reset ?