Re: pci power management !!

[Gary Solomon <Gary_Solomon@ccm.jf.intel.com>]

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     When functions are in D0(active), D1, D2, or D3hot states there should 
     never be a bus segment reset during normal operation.  Believe that 
     this would be indicative of a pretty significant system failure, and at 
     this point all functions on the bus segment would be transitioned 
     simulataneously to D0uninitialized (all functional context lost).
     
     From standpoint of PME context, only those functions that are designed to 
     operate from D3cold/B3 are required to maintain PME context through bus 
     reset sequences.  A function that supports PME# from states other than 
     D3cold is required to maintain PME# context during transitions from 
     whichever states they support to D0uninitialized.  However these 
     transitions would be affected through class/device/bus driver interactions 
     with full power to the bus at all times, and with NO assertion of PCI RST#.
     
     On second question regarding distinguishing between a power-on-reset and a 
     bus segment reset....
     
     PCI bus segment reset will occur during power up, and any other time that 
     the PCI bus is brought from B3 to B0 (i.e., resume from ACPI S3, S4, or S5 
     process).  A new requirement for RST# (documented in PCI SIG-ratified 
     3.3Vaux ECR) requires that systems supporting 3.3Vaux will assert and keep 
     asserted PCI RST# while the bus is in B3.  Functions designed to operate on 
     3.3Vaux determine, from sampling occurence of trailing low to high edge of 
     RST#, that bus power has been reapplied and it is now time to transition to 
     D0uninitialized.  This requirement eliminates potential mistaken identity 
     of a powered off bus with RST# floating at or near ground vs. an actual 
     assertion of reset.  Functions powered from 3.3Vaux depend on this 
     requirement.  All other functions that are not powered by 3.3Vaux see no 
     difference in bus behavior.
     
     Hope this helps.
     
     Regards,
     
     Gary Solomon - Intel
     
     

______________________________ Reply Separator _________________________________
Subject: pci power management !!
Author:  pci-sig-request@znyx.com at SMTPGATE
Date:    3/11/98 7:02 PM


* The PCI Bus Power Management Interface Specification Version 1.0,
  Chapter 5 talks about PCI function power management states.
  If the function is in state D3 and supports PME# generation, and 
  a bus segment reset (RST_N#) occurs the PME context have to be 
  maintained. If the function supports PME# generation from other
  states like D1 or D2 and in case a bus segment reset(RST_N#) happens 
  when in these states is it required to maintain the PME context? 
  Spec. is not clear about this. Can someone clarify?
     
* How to differentiate a power-on-reset and bus segment reset ?

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