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Re: Big and little endian issues
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Big and little endian issues
- From: Kevin.Normoyle@Eng.Sun.COM (Kevin Normoyle)
- Date: Thu, 23 Apr 1998 09:50:36 -0700
- Resent-Date: Thu, 23 Apr 1998 10:20:28 -0700
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One problem I see in the "software guys vs hardware guys" discussion
on little/big endian swapping/noswapping.
Hardware guys see buses that transfer multiple bytes in a single
cycle.
Byte 0 may be on the left or right side of this bus, which
may be 32, 64 or 128 bits wide, say.
To achieve the software-visible goal of no-swapping, i.e. a single
byte load of address 0 refers to the byte at address 0 everywhere,
the hardware guys have to "swap".
If you told a hardware guy "don't swap", then the software guy will
see an effective swap, which will vary depending on the different bit widths
between the beginning, intermediate, and ending buses, and whether they
are individually mapped as big or little-endian.
This is because the hardware guy typically thinks about the routing of the bits,
not the logical behavior of swap vs no-swap (i.e. the byte mapping).
I agree that the problem is that the software guy knows what he wants,
and the problem is getting the hardware to understand what he has to do
to achieve that.
A simple "no-swap" comment doesn't get you what you want.
Anyone who's implemented a byte-invariant little plus big-endian system
will see what I mean. (hopefully).
-kevin